1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device with a buried bit line and a method for fabricating the same.
2. Description of the Related Art
Most semiconductor devices include transistors. For example, in a memory device such as a DRAM, a memory cell includes a cell transistor such as a MOSFET. In general, in the MOSFET, source/drain regions are formed in a semiconductor substrate, so that a planar channel is formed between the source region and the drain region. Such a general MOSFET is called a ‘planar channel transistor’.
Since it is necessary to continuously improve the degree of integration and performance of a memory device, a fabrication technology of the MOSFET has reached a physical limit. For example, as the size of a memory cell is reduced, the size of the MOSFET is reduced, so that the channel length of the MOSFET is also reduced. When the channel length of the MOSFET is reduced, the characteristics of the memory device are degraded due to various problems such as degradation of data retention characteristics.
In order to increase the channel length, a vertical channel transistor (VCT) has been proposed. The vertical channel transistor includes a pillar in which a vertical channel is formed. A source region and a drain region are formed at the upper portion and the lower portion of the pillar. One of the source region and the drain region is connected to a bit line.
FIG. 1 is a diagram illustrating a semiconductor device in the conventional art.
Referring to FIG. 1, a plurality of bodies 12, which are separated from each other, are formed in a semiconductor substrate 11. A pillar 13 is formed vertical to the surface of the bodies 12. A buried bit line 14 is buried in the body 12. The pillar 13 includes first and second source/drain regions 16 and 18 and a channel region 17. A word line 15 extending in a direction crossing the buried bit line 14 is formed at the sidewall of the pillar 13. Since the word line 15 has a vertical structure, a vertical channel is formed. The first source/drain region 16 may also be formed in the body 12.
In the conventional art of FIG. 1, the semiconductor substrate 11 is etched by considering the height of the pillar 13 including the channel region 17, so that a preliminary body line is formed. Then, the upper portion of the preliminary body line is etched to form the pillar 13. The lower portion of the pillar 13 becomes the body 12.
In the conventional art, in order to substantially prevent punch-through (refer to a reference numeral ‘P’) between adjacent buried bit lines 14, it is necessary to ensure a predetermined height (refer to a reference numeral ‘P1’) at the lower portion of the buried bit line 14. The height P1 for substantially preventing the punch-through is about 80 nm to about 90 nm inclusive of the depth of the first source/drain region 16 formed below the buried bit line 14. Therefore, since the total height (a reference numeral ‘H’) of the body 12 and the pillar 13 is very high, a high aspect ratio etching process is required when forming the preliminary body line.
As a consequence, in the conventional art, since it is necessary to consider the height of the body 12 and the pillar 13, the high aspect ratio etching process is required. Moreover, since an aspect ratio is further increased in order to substantially prevent the punch between the adjacent buried bit lines 14, pattern leaning occurs.
In addition, in the conventional art, an interval between the adjacent buried bit lines 14 is increased, but there is a limitation in reducing parasitic capacitance between the adjacent buried bit lines 14. That is, the area of the first source/drain region 16 connected to the buried bit lines 14 has an influence on the parasitic capacitance. Therefore, a facing area (a reference numeral ‘P2’) between the adjacent buried bit lines 14 includes the first source/drain region 16, resulting in an increase in the parasitic capacitance.